A SERDES (an acronym standing for SERializer/DESerializer) is a component in a digital communications path that converts data from a multi-bit parallel channel into equivalent data that is then applied to a higher speed serial channel. Typically, the communications path is bi-directional, and to accommodate that a SERDES also converts data from the serial channel into equivalent data that is then applied to the parallel channel. Multi-bit parallel channels (as found in parallel bus architectures) often present performance difficulties when operated at high speeds over long distances. For example, there may be skew between the bits. A serial channel is often easier to operate, even at much higher speeds. A common use of SERDES circuits then, is to use them in pairs, one SERDES at each end of a xe2x80x9clongxe2x80x9d communications path that is parallel at each end, but serial in-between.
So, for example, a high speed interconnecting serial channel might operate at 2.5 GHz and be a differentially driven pair of transmission lines, or a fiber optic link, while the two parallel ports might be eight bits wide with a word rate of 250 MHZ. Viewed from afar, the SERDES is part of a (transparent) SERDES to SERDES connection that forms a (possibly long) eight bit parallel path clocked at 250 MHZ. (It will be noted that the information, or overall bit rate, in the interconnecting serial channel is higher than that for the parallel data being transported. Some of that extra capacity is used to facilitate serial channel xe2x80x9chousekeepingxe2x80x9d and will be of considerable interest in due course.) A typical application for such a pair of SERDES circuits is as transmitting and receiving mechanisms for high speed data paths between individual ICs (Integrated Circuits) located on the same printed circuit board, or perhaps located on different printed circuit boards within the same chassis and interconnected through a backplane. (There are, of course, other applications for SERDES circuits, but these are the ones of our immediate interest.) In such an arrangement a pair of SERDES circuits forms an essentially transparent mechanism that transports eight-bit words from one location (an IC or other environment) to another, as if accomplished by a bus, but without certain practical difficulties (e.g. bit-to-bit skew) that beset a bus operating at high frequencies.
For various reasons the high speed serial data (one bit wide) is sent as a differential pair. These reasons include speed of detection at the receiving end (twice the dv/dt is experienced by the differential receiver), common mode rejection by the receiver of noise induced in both sides of the signal, and noise generation avoidance through zero net change in currents flowing through ground and the power supply. What is more, each signal of the differential pair is often AC coupled. This allows SERDES of different manufacture or incompatible semiconductor families to cooperate. Typically, 4.7 uF capacitors are disposed on the PC board and are in series with the differentially driven transmission lines that couple the serial ports of the SERDES.
We have already indicated that the serial and parallel paths do not have the same bit rates: in the example set out above, eight times 250 M is not 2.5 G; there is a ten-to-one difference, instead of an eight-to-one difference. The difference in bit rates is accounted for by the use of a mapping that uniquely associates each of the possible two hundred and fifty-six eight-bit parallel bit patterns (it will be convenient to refer to these as xe2x80x9ccharactersxe2x80x9dxe2x80x94even if those bit patterns do not represent familiar alpha-numeric or typographical symbols) with a different serial pattern of ten bits, of which there are one thousand twenty-four. The mapping is an industry standard informally-called 8b10b, and the xe2x80x9csurplusxe2x80x9d seven hundred sixty-eight serial characters are used in various ways, among which is the definition of an entire class of control characters used for supervisory purposes in managing the operation of the serial channel. It will be noted that the mapping mechanism needs to be bi-directional, since a receiving SERDES needs to convert the ten-bit serial characters back into eight-bit parallel characters. At the block diagram level this mapping mechanism turns into an 8b10b encoder and a companion 10b8b decoder.
An important aspect of the 8b10b mapping is that it allocates to each pair of eight-bit parallel characters a pair of ten-bit serial patterns that, over the pair, has the same number of ones and zeros. Such balance is needed to keep the AC coupling in the high speed serial path from accumulating a charge (blocking) and subsequently attenuating the amplitude of the transmitted signal. Otherwise, there would exist sequences of eight bit data that would produce corresponding ten-bit sequences that were unbalanced, which if they are long enough, would charge the coupling capacitors completely, resulting in a serial channel malfunction.
Unfortunately, there are only two hundred fifty-two ten-bit characters that have five ones and five zeros, which means that a simple 8b10b scheme would have four eight-bit parallel characters that are associated with unbalanced serial characters. Long input sequences involving those particular parallel characters would be untenable, so the actual 8b10b scheme is xe2x80x9ccontext sensitivexe2x80x9d and alters the mapping, as needed, on alternate characters such that serial side is always balanced over at most twenty bits (corresponding to two input characters). This involves what is called a xe2x80x9cdisparity bitxe2x80x9d and is a known mechanism. A related issue is the fact that no clock signal is explicitly sent from the transmitting SERDES to the receiving SERDES. Instead, the receiving SERDES performs clock recovery. While AC coupling requires balance, clock recovery benefits from regularly distributed transitions in the data, with the implication that some mappings from eight bits to ten bits are less desirable than others.
Operating in cooperation with the basic 8b10b encoding and 10b8b decoding is the coding and decoding of ten-bit framing characters that are periodically inserted in the serial traffic as part of an established SERDES protocol. This mechanism (packets separated by framing characters), in conjunction with initial training sequences and the practice of clock recovery, allow the receiving SERDES to xe2x80x9csync upxe2x80x9d on the transmitting SERDES; both a frequency locked-loop and a phase-locked loop are involved. The tasks of generating and of recognizing such control characters are facilitated by defining the often used serial channel control characters (of which the xe2x80x9ccommaxe2x80x9d K28.5 is one member of that family of characters) as some consecutive number of ones followed by some consecutive number of zeros, including the one""s complement of those patterns. The patterns selected for this duty are five consecutive ones followed immediately by two consecutive zeros, and five consecutive zeros followed immediately by two consecutive ones. It turns out that this can be accomplished by assigning such meanings to otherwise unused xe2x80x9csurplusxe2x80x9d codes in the 8b10b scheme.
Now let us consider the issue of testability for large and complex printed circuit board assemblies having many ICs, such as the router cards and line cards found in industrial strength internet routers. It will be appreciated that some manufacturer""s versions of those include pairs of SERDES, as described above.
A venerable prior art method of testing installed ICs involves a xe2x80x9cbed of nailsxe2x80x9d that makes electrical contact between a test apparatus and useful locations upon a DUT (Device Under Test), which in this case is a printed circuit board assembly. Further connections are made to the lands of the edge connector(s) and any cables attached to the board. The test apparatus applies power, stimulus, and makes measurements. However, trends occurring over the last few decades have limited the applicability of such testing. These include high numbers of tiny traces, traces on interior layers of multi-layer boards, and high frequencies of operation that cause circuits to react unfavorably to the parasitic impedances added by the test fixture. And while testing with a bed of nails remains a staple in the electronics industry for a certain class of printed circuit board assemblies, another approach has recently emerged to aid in the testing of, and diagnosis of failures in, large complex printed circuit board assemblies. It goes by the name xe2x80x9cboundary scanxe2x80x9d and amounts to the inclusion within ICs of a limited, but quite useful, amount of internal testability circuitry that can be exercised by an external tester.
The boundary scan technique was developed by a group of interested manufacturers that formed a group called JTAG (Joint Test Action Group). This effort eventually resulted in an industry standard formalized as IEEE 1149.1, which runs to well over two hundred pages. We are quite interested in the boundary scan technique that is set out therein, and shall attempt to summarize certain pertinent concepts in the next few paragraphs. At that point we shall be in a position to appreciate xe2x80x9cwhat the problem isxe2x80x9d and get on with a summary and a description of the invention. But for now, just as we did for SERDES circuits above, we must engage in a brief digression about the nature of the boundary scan technique.
The fundamental idea of boundary scan is to be able to put an IC into a mode where its external connections (those at the xe2x80x9cboundaryxe2x80x9d) are xe2x80x9cdisconnectedxe2x80x9d from their normal core IC circuitry, and are instead coupled to the aforementioned internal test circuitry. That internal test circuitry includes a collection of boundary scan registers and a supervisory controller operated through a TAP (Test Access Port) having five electrical signals. Associated with each IC pin that is to be included in the boundary scan tests (but excluding the pins for the five signals of the TAP) are one, two or three one-bit registers located within that IC. The number of such registers depends upon the functionality of the associated pin: input-only or output-only (one), tri-stated output (two), or bidirectional (three). According to the circumstances, one of these registers indicates if the pin is to be active (as either a driver or a receiver) or if it is instead to be neither (tri-stated), one indicates output data to be driven, and the other indicates input data received. This selective coupling is accomplished by MUXs (multiplexers) between an IC pin and its respective sets of registers (for boundary scan testing) and its respective core IC circuitry (for normal operation). The boundary scan registers and these MUXs are coupled to, and are controlled by, a small finite state machine of sixteen states that requires about two hundred gates to implement. The boundary scan state machine gets its orders from, and reports its results to, external test apparatus that communicates with the finite state machine via the five signals of the TAP.
The five signals of the TAP interface are: TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and TRST (Test Reset). In the typical case where there are several ICs on the circuit board, TCK (and perhaps TRST) can be signals common to all of the ICs through a single instance of each signal. There is defined a way where TMS essentially functions to perform an xe2x80x9cenable boundary scan for this chipxe2x80x9d operation that provides unit selection and substitutes for addressability. That, in conjunction with a pass-through (internally from TDI to TDO, via a bypass scan register) allows the daisy chaining of TDO from one IC to TDI of the next, and so on, so that the number of added pins to the circuit board needed for support of the boundary scan technique does not swamp its usefulness, even for large numbers of ICs on the board. By using the unit selection ability and the loop formed by the daisy chain, the following types of test operations can be performed under the aegis of the external test apparatus.
Within a given IC, the status of each pin can be specified. If a pin is to be internally driven, a logic one or logic zero can be specified. If a pin is to be externally driven, then the received value can be latched. A pin can also be tri-stated. The value of all pins can be reported to the external test apparatus by a serial shifting out onto TDO of the received value registers. An internal loop-back arrangement allows the boundary scan circuitry to measure, as in reception, its own attempts to drive a pin, which is also reported. In this connection, the sensing of an output pin is performed one driver stage back from the actual ohmic connection to the PC board, so that, say, a short to ground on that line will be sufficiently decoupled that it will not thwart a correct measurement of the attempt to drive. The idea is that we want a rough preliminary assessment of the health of the drivers and receivers of the IC, and are patient enough to wait to discover such an external short with subsequent testing performed in due course.
Once we are satisfied that all the ICs have operational boundary scan abilities, we can then use those to determine if the interconnecting traces between ICs are free of faults. This is done by telling the boundary scan mechanism in one IC to drive with specified patterns of ones and zeros those lines leading to other ICs and then having those ICs report the results. By properly selecting the values driven, traces (including their attendant solder joints) can be tested for continuity, shorts to ground or VDD, and shorts to each other. Given the high density of small surface mount parts on today""s PC boards, that some PC boards are huge (a square foot is not uncommon), the frequent use of multi-layer techniques and inaccessible solder joints such as in ball grid arrays, such verification of proper connectivity is no small matter.
Once proper connectivity has been established, the boundary scan mechanisms can be turned off and further functional testing performed using other means, with the expectation that a correct diagnosis of a failure will now be considerably easier to perform.
Those concerned with boundary scan operation tend to think of it as if it were DC testing. To be sure, if one were to put a scope probe on an IC pin, a changing waveform would often be observed. But in reality, an IC pin is statically driven with a particular logic state (a DC event) until changed in accordance with the next step in a test algorithm. And while in principle, that type of boundary scan operation is perhaps more aptly termed xe2x80x9cstaticxe2x80x9d boundary scan, xe2x80x9cDC boundary scanxe2x80x9d has instead become the customary accepted terminology. Accordingly, we shall from time to time find it convenient to refer to xe2x80x9cDCxe2x80x9d boundary scan when appropriate.
The fact that changes occur frequently with DC boundary scan must not be confused with genuine AC operation, particularly since there has recently emerged an xe2x80x9cAC boundary scanxe2x80x9d technique. What distinguishes it is that the driver circuitry associated with its boundary scan operation generates transitions and that the associated receiver circuitry is responsive to those transitions. The idea is to tolerate AC coupling in the path between the driver and the receiver. Typically, some clock signal is used to produce the transmitted transitions and a selected phase shift is applied to one of the transmit or receive processes to change the expected voltage level of the received result. In this way the AC boundary scan technique can verify that both logic ones and zeros can be exerted, even though there may be intervening AC coupling in the path between the pins being tested. It will be appreciated that the transition sensitive nature of AC boundary scan requires more involved circuitry, and is perhaps somewhat xe2x80x9cfussyxe2x80x9d and less reliable when compared to DC boundary scan.
And thus we come to two problems encountered when the boundary scan technique is to be applied to a SERDES, either as a stand-alone IC, or to one that is incorporated as an addition into an IC having some other principal function. The first problem is that the differential driver that drives the pair of transmission lines (or perhaps instead drives an optical source) operates at such a high frequency that it is generally not tolerable for there to be an intervening MUX that controls whether the differential driver drives data provided by the chip core or by the boundary scan mechanism, whether AC or DC. The relatively slow boundary scan mode of operation would likely work, but the very high speed path for data originating at the chip""s core would be corrupted beyond usability. The second problem is the presence of AC coupling in the high speed path between SERDES of different ICs. This prevents a xe2x80x9cDCxe2x80x9d output stimulus from one SERDES from being a DC input stimulus to the other SERDES. That in turn prevents the PC board trace corresponding to that path from being tested via DC boundary scan. AC boundary scan is not appropriate either, owing to its use of the aforementioned MUX (the first problem).
Now, suppose a purveyor of fine SERDES circuits offers to fabricate ICs consisting of, or including, such SERDES for use in complex printed circuit board assemblies (e.g., router cards and line cards), perhaps assembled by a second party for use in an item sold to a third party. These SERDES may or may not use AC coupling in their interconnecting serial channel; if they do then that prevents use of DC boundary scan, while the need to use a MUX eliminates both AC and DC boundary scan, anyway. While the ICs at issue can be variously tested when they are made, but prior to installation, that does little toraid in the diagnosis of assembled printed circuit board assemblies that fail during their testing (conducted perhaps, in an altogether different factory). If the ICs at issue cannot perform a full boundary scan owing to an exemption for the serial channel of the SERDES section, then additional uncertainty is created during the testing and troubleshooting process. Such uncertainty has an economic cost, and is otherwise undesirable. It would thus be desirable if there were a convenient and cost effective way to allow a SERDES to participate in the DC boundary scan test techniques described by IEEE 1149.1.
The problem of implementing DC boundary scan for the interconnecting AC coupled serial channel between a source SERDES and a destination SERDES includes substituting, during a boundary scan test mode, selected test mode traffic in place of the normal mission mode traffic. During normal mission mode operation eight-bit parallel character mission mode information is replaced with corresponding conventional ten-bit parallel bit patterns by an 8b10b encoder. These ten-bit parallel patterns are serialized by a parallel-to-serial converter, sent over the serial link and received by a serial-to-parallel converter that produces a received ten-bit parallel code. The received ten-bit parallel codes are applied to an 10b8b decoder, from which the originally applied eight-bit mission mode characters are recovered. During the boundary scan test mode operation what corresponds to the mission mode""s eight-bit parallel characters are signals originating in the boundary scan environment representing the desire to transmit a boundary scan DC value of one (a xe2x80x9cBS1xe2x80x9d) or a boundary scan DC value of zero (a xe2x80x9cBS0xe2x80x9d). Ideally, the serialized bit patterns selected to represent BS1 and BS0 would be single characters that are frame alignment characters and that each contain an equal number of ones and zeros. Unfortunately, the 8b10b encoding scheme does not include such a combination. The serialized bit patterns sent over the serial link to represent BS1 and BS0 are each of twenty bits in length, as if they each had been represented by some respective pair of eight-bit parallel characters that were encoded into, and subsequently decoded from, a pair of ten-bit parallel bit patterns. Each of the pairs of ten-bit (serial or parallel) bit patterns involved in this boundary scan test mode operation are chosen to contain a frame alignment character and an associated disparity equalization character. This preserves DC line balance within the AC coupled serial channel, respects the disparity bit mechanism used by the SERDES, facilitates clock recovery and frame alignment, even for asynchronously transmitted BS1""s and BS0""s. If receiver tolerances for frame locking and disparity tolerance permitted it, single characters could represent BS1 and BS0. This is an area of operation not contemplated by the standards for SERDES circuits, and interoperability between products from different vendors could well be problematic. There is no such difficulty with the paired character technique, as it does conform to operation contemplated by the standard, even though its ultimate purpose is outside the scope of the standard.
In a first preferred implementation the existing 8b10b encoder of the source SERDES and the 10b8b decoder of the destination SERDES are left unaltered, but during boundary scan test mode operation they are disconnected from their respective parallel-to-serial and serial-to-parallel converters by respective source and destination MUX""s controlled by a signal representing the mode of operation: mission mode or boundary scan test mode. During the boundary scan test mode operation an indicated BS1 or BS0 is encoded by separate circuitry into respective pairs, each of two consecutive ten-bit parallel words that are then applied by the source MUX to the native parallel-to-serial converter of the source SERDES. The resulting twenty-bit serial bit patterns are transmitted over the serial link to the native serial-to-parallel converter of the destination SERDES. The received pair of ten-bit parallel bit patterns are then routed by the destination MUX, not to the native 10b8b decoder, but instead to separate circuitry in the destination SERDES that decodes the received ten-bit parallel bit patterns into whichever one of BS1 or BS0 was originally sent. Signals representing this received information are then applied to appropriate associated boundary scan circuitry in the destination SERDES.
A second preferred implementation includes providing native 8b10b encoders and 10b8b decoders which directly recognize, in place of the MUX""s of the first preferred implementation, that the boundary scan test mode is in effect. During the boundary scan test mode, but not during the mission mode, the 8b10b encoder in the source SERDES is additionally responsive to an indicated BS1 or BS0, and itself provides the associated twenty-bit parallel bit pattern, which is then serialized and transmitted in the normal manner. At the destination SERDES the received twenty-bit serial pattern is converted back to parallel and applied as consecutive words to the 10b8b decoder, which will output separate individual signals representing BS1 and BS0, in place of the normal eight-bit parallel characters of the mission mode. The signals representing BS1 and BS0 are then applied to appropriate associated boundary scan circuitry in the destination SERDES.
These solutions avoid placing MUX""s in the sensitive high speed path of the serialized data. That allows normal data to be handled transparently and without corruption, while permitting the use of AC circumstances to substitute for DC conditions in the synthesis of a boundary scan operation.